NVIDIA's adaptive memory timing patent explained

Hardware NVIDIA Files Controller-Adaptive 1T/2T Memory Timing Patent Application
Michael Schuette - May 19, 2006 1:54 PM

Forward from the EIC: Michael Schuette is the founder and owner of LostCircuits.com, as well as the Vice President of Technology Development for OCZ Technology. OCZ Technology is an advertiser for DailyTech.

On May 11 2006, the US Patent Office published a pending patent application submitted by NVIDIA on 11/11/2004 on a memory controller adaptive 1T/2T timing control. This publication has set off a few discussions about what NVIDIA might be trying to do there, particularly since the publication of the patent application coincides with the announcement of NVIDIA's Tritium overclocking technology and SLI memory platform.

The first thing that needs to be mentioned in the context of the publication is that this is a publication of a pending application and does not constitute the granting of a patent. Nonetheless, the publication covers a rather interesting invention and - in order to dispel some of the myths floating around - it is worth looking at what this invention is really all about.

To start with the basic technical background, the command rate that is the center point of the application defines the rate at which the address and command unit in the memory controller is able to generate controls and addresses. A 1T rate means that on every clock an address and command can be generated. A 2T rate means that addresses and commands can only be issued on every other clock with one wait state in between.

Without interleaving, the CMD rate hardly makes a difference since the execution of a Row activate or even a Read command will take a minimum of 2 cycles anyway before the next address or command can be given. However, bank interleaving allows to keep multiple pages open at the same time or, by extension, to open multiple pages quasi-simultaneously, meaning that the bank activate commands are issued back-to-back. In this case, there is a clear advantage for using a 1T command rate.

Likewise, in a DDR2 architecture, the posted CAS feature allows the issuance of a read command immediately after a bank activate command and the needed latency cycles are added internally on the memory device in the form of a preprogrammed added latency. In this case, a 2T CMD rate will also have some impact on bandwidth and latency since it increases the CAS latency by one cycle over the nominal value.

The command rate is largely defined by the distributed capacitance of the memory subsystem. That is, each memory chip has a given capacitance that will increase with the density of the chip itself. Given the fact that currently used DIMMs can range anywhere from 128 MB to 2 GB (in consumer systems) the distributed capacitance of the system as seen by the address and command bus can also vary by a factor of 16 on a single slot basis. Adding multiple slots to a system increases the scaling factor further.

Increasing capacitance adds increasing load on the "sender", in this case, the address and command unit of the memory controller. Increasing load means that a stronger signal is needed to broadcast the signals and the conventional cure for the situation has been to scale the drive strength according to load by means of variable output buffers.

Needless to say that a process as fundamental as that mentioned has already been covered by multiple patents, for example USPN 7032058 and USPN 6684263, both issued to Rambus and having a priority date of October 19, 1999 show similar adjustments of parameters according to bus topology

NVIDIA's new invention goes a different way. In a nutshell, two redundant memory controller address and command units are used that are cross-linked. Under normal operating conditions, one of the units is silent, however, in situations of increased load (more memory), the second unit is activated and aids in driving the addresses and commands across the bus. This way, the two units may act like a zipper where both strings are operating at 2T CMD rate but will achieve a combined operation at a 1T rate even with high memory densities. The invention further takes into account the operating frequency and adjusts the command rate accordingly.

In general, the new invention is applicable to all memory subsystems, however, at this point, the primary target application appears to be the graphics card sector in that a single controller (combo) will scale across a wide range of memory subsystem configurations without performance degradation. With respect to system memory controllers, it is necessary to keep in mind that most of them will be integrated on the CPU in the future, and of course, this may open up licensing opportunities for NVIDIA - all of this pending the question of how many of the claims will be allowed in the final issuance of the patent.